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The frequency at which transmitted power has dropped to 50 percent of the injected power is called the "3 dB" point and is used to define the bandwidth of the interconnect. This is the highest sine wave frequency at which the interconnect can be used. For some applications, more than 3dB may be acceptable, in other applications, less than 3dB will be acceptable. 3dB drop in power corresponds to a drop of 30% in voltage amplitude. This is the noise margin in most device families. If a signal were to drop by 30% in amplitude, it would most likely not meet specifications, so the criterion of 3dB is reasonable for digital microcircuits. Distortions in the interconnect decrease the bandwidth of transmitted signals and increase rise-times of transmitted signals. Distortion of the pristine waveforms coming from the junctions is caused by on-chip metallization, packaging, and interconnects which creates parasitic capacitance, inductance and resistance. This distortion limits the rise-time of signals that propagate in the interconnect environment, increasing the minimum possible clock period. Distortion from packages and interconnects can be so severe as to cause false triggering. Rise-time degradation and clock skew can slow the operating clock frequency below the specified value. As the clock frequency and interconnect density increase, it becomes harder for the interconnect system to maintain the signal integrity within acceptable levels.

Rise-Time Degradation

A decrease in the bandwidth of a signal causes an increase in the leading edge rise-time. This rise-time degradation will introduce a delay until the voltage level reaches the triggering threshold, which increases the effective wiring delay.


The clock frequency does not determine the bandwidth, the rise-time of the signal does. In digital microcircuits, there is a connection between rise-time and clock frequency. As the rise-time drops, this is an indication that the microcircuit is capable of switching faster, and the clock frequency usually increases. Depending on the type of digital system there are between 5 and 10 rise-times per clock period.

Noise Level

An acceptable noise level is a major concern for interconnect designs. The interconnect transports the signal to and from each node with an acceptable level of distortion, and also transports the DC power and ground to all the microcircuits with an acceptable noise level. The criterion of what is acceptable noise comes from the noise margin of the microcircuit family. The noise margin is the difference between the worst case output voltage and the minimum acceptable input voltage. There are three primary sources of noise: signal integrity down a single trace, crosstalk from adjacent lines, and switching noise from the power and ground distribution.


Ringing can become a significant problem at higher bandwidths.  It can be eliminated by placing a damping resistor at the source.  Another suppression technique is to use ground planes in packages to minimize leadframe inductances and to control the impedance of interconnect traces. In addition, series damping resistors may be added to the circuits in such a way as to avoid an added hit from RC delays. Ringing and reflection noise increases in magnitude as the bandwidth of the signal increases and the rise-time decreases; therefore most high-speed microcircuits have the option of using reduced slew rate output buffers so the packaging does not seriously degrade the signal integrity. A longer spatial extent will make the signal less sensitive to interconnect imperfections.

Crosstalk Noise

Crosstalk noise is due to capacitive and inductive coupling between two traces. When two traces run parallel to each other, there is the possibility of coupling voltage from one to the other. The line that is generating the noise is termed the active line or aggressor and the trace on which the noise appears is termed the quiet line or victim line. The magnitude of the coupled noise, Vquiet/Vactive, depends on:

a. The pitch between the traces

b. The characteristic impedance of the traces

c. The dielectric constant of the material surrounding the traces

d. The fraction of the length of the quiet line over which the traces are adjacent

The noise allocated for near-end crosstalk is typically about 3%. A lower dielectric constant for the same pitch will decrease the crosstalk. With FR-4, a 50-Ohm microstrip has a linewidth about twice the dielectric thickness. To keep the crosstalk below 3%, the spacing should be at least 4x the dielectric thickness. In asymmetric strip line, the lower dielectric thickness is about equal to the linewidth for 50 Ohms. To keep the crosstalk to less than 3% requires spacing about 2x the lower dielectric thickness.

Simultaneous Switching Noise

Simultaneous switching noise (also called, ground bounce, or delta I noise) causes a problem in packaging high-performance CMOS microcircuits. This is due to the inductance of the power and ground distribution to the chips and the transient current from output buffers. All of the inductance of the power and ground distribution traces, from the chip to the nearest decoupling capacitor, must be included. In simultaneous switching, it is the inductance associated with the ground connection of the chip bonding, such as the wirebond and leadframe, that plays the most critical role. Usually, a number of buffer gates are tied to the same ground rail. In leading edge CMOS microcircuits, the number of gates switching simultaneously is increasing and the switching transition time is decreasing. Both of these effects are increasing the impact of simultaneous switching noise. Minimizing this problem requires solutions that address:

a.  The chip drivers: All high-speed gate arrays currently have available the option of selecting a slower output buffer slew rate to decrease the bandwidth of the output signal.

b.  The number of outputs sharing the same ground line: Though there is a minimum number of power and ground pads that must be used on a chip, the designer has the option of adding more. The trend is to appropriate all unused, available pads for extra power and ground. This approach has the double benefit of reducing the inductance associated with the power and ground connections and decoupling sensitive gates from their neighbors. For 50MHz ASICs, minimum guidelines call for one ground for every 16 gates.  This number is rapidly approaching one for every four output buffers in 200MHz ASICs. This is another driving force causing increases in the off-chip pin count.

c.  The inductance of the chip attach: It is the inductance of the ground path section of the circuit that influences the switching noise. The inductance of the package leadframe and chip bonding can be decreased. Ground planes in the Packages are the first step to decrease leadframe inductance. Chip bonding inductance can be decreased by designing shorter wirebond lengths or by using flip chip. This is a strong driver for the use of flip chip die attaches. Decoupling capacitors can be attached as close as possible to the chip, either on the multilayer package or directly under the chip package.

d.  The output capacitance that is driven: The capacitance that must be driven by each buffer can be decreased as a spin-off of higher packaging efficiencies driven by higher clock frequencies.

Ground Leads

Shortening ground leads by bringing them to the center of long packages, and bringing high current carrying signal leads in proximity to the ground leads can dramatically reduce switching noise. This change reduced the effective inductance of ground leads by a factor of 5 between the old and the new pinouts.

High speed problems.

There are four design guidelines that should minimize 80% of high-speed problems:

a.  Keep the interconnects as short as possible. This will minimize delay times, clock skew and signal integrity problems.

b.  Use controlled impedance interconnects, at roughly 50 Ohms characteristic impedance. This minimizes reflection noise and keeps EMI low.

c.  Keep adjacent traces far enough apart so that crosstalk is below the specification, typically 3% coupling or less.

d.  Keep the impedance of the power and ground distribution low, using planes where possible. Keep all leads as short as possible to reduce switching noise.

Timing Errors

Timing errors need to be avoided when designing high-speed applications. Excessive propagation delay or race conditions are the cause.  Excessive propagation delay is when the propagation delay of a circuit is longer than the clock period. A race condition occurs when a gate does not have all its inputs when needed, compared to the clock, because other gates were switched either too late or too early due to clock skew. Being able to predict and control clock skew to less than one gate delay is of great importance. Within one clock cycle, the number of gates that must switch sequentially is called the logic depth, N logic depth. This is typically 10 to 20. The length of time it takes for the signal to propagate through the longest path will establish the shortest clock period. In a system with a 50MHz-clock frequency, typically 5 to 10 percent of the nets are critical in that their total propagation delay may approach the clock period. In very high-speed systems with clock frequencies above 100MHz, 20 to 50 percent of the nets could be critical. The propagation delay of a net will depend on the delays associated with each part of the net: the gate delays, the on-chip interconnect delays, the output buffer delays, the delays associated with the packages, and the wiring delays between packages.


Interconnects at low frequency are effectively transparent and no special design rules are required; however, interconnects at high frequency do need special care.  Described below are three effects that may arise and prevent an application from working.

a.  Exceeding the timing margin from race-conditions between the data stream and effects that may arise that will prevent the design from working.

b.  Exceeding the noise margin from:

1) waveform distortion and decreased signal integrity

2) crosstalk between adjacent traces

3) noise in the power and ground distribution system, such as ground bounce  and simultaneous switching noise or IR drop

c.  Exceeding the EMI margin by common or differential mode radiation

Manufacturing & Assembly Issues

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Gold and aluminum are two types of wire typically used for wirebonding. Each has a different assembly process, equipment and operating conditions. The metallization on the chip is typically aluminum and the metallization on the second pad is typically gold or silver plated copper. The bonding is performed at room temperature and the weld is accomplished with pressure and ultrasonic energy. When just heat and pressure is used the process is termed thermocompression bonding. In order to form a reliable gold-aluminum bond, the joint temperature must be in the 300-400°C range. This is suitable for ceramic packages using a Si-Au eutectic die attach but is too hot for plastic packages. When lower temperatures are required, the addition of ultrasonic energy reduces the temperature required for reliable joint formation to 150-200°C. This process is termed thermosonic bonding. In addition to the temperature difference between gold and aluminum wirebonding, the other chief difference is the speed of the bonding.

Gold Thermocompression Bonding

Gold thermocompression bonding is 3 - 5 times faster than aluminum wedge bonding. The speed advantage is due to the nature of the motion of the tool and the substrate. When the ball-bond is formed on the die, the tool can move off in any direction to make the second bond. The package or substrate can be stationary and the tool goes back and forth. This means the bonding process is limited by how fast the tool can move from pad to pad. High-speed bonders can process 10 bonds per second.

Aluminum Wedge Bonding

For Aluminum wedge bonding the tool is directional. The first and second wedge bond must be done in the direction of the wire. In most packages, the wirebonds fan out. After each bond is made the tool head must be rotated slightly. This slows down the bonding process to only about 3 bonds per second. When the bonds are parallel, and the tool does not have to rotate, ultrasonic aluminum wedge bonding will be faster than 3 bonds per second.

Chip bond

Important electrical properties of the chip bond are lead inductance and resistance. The most important influence on the lead inductance is length. The shorter the interconnect, the lower the inductance. Lower inductance in the power and ground path will decrease ground bounce and switching noise. The second important term is resistance. Resistance will affect the DC voltage drop in power and ground paths. A wirebond, 1mil in diameter has a resistance of about 1 Ohm/inch. For a wire 50 mils long, the resistance is about 50 mOhms. With the typically 0.25 A limit for a single wirebond, the DC voltage drop might be 12 mV, below the typical noise budget for even a 3 V system. Shorter lengths and wider cross sections contribute to lower resistance. Typical electrical properties of various interconnect are summarized in Table 3.

Table 3. Summary of Electrical Properties of Chip Bonding


Resistance Per Length

Inductance Per Length


Typical Lengths


Typical Resistances

Typical Inductances


1 Ohm/inch












Flip Chip


0.08 Ohms/inch



< 1mOhm

< 0.1nH

Pad Counts

Pad counts for die continue to increase. This comes from the combination of increased functionality and gate count, and the need for more power and ground pins to minimize ground bounce. The die-size for the same gate count is decreasing as the feature size gets smaller. These factors contribute to the need to decrease the pad pitch required around the periphery of a die for bonding pads. For example, the Pentium chip has maintained the same functionality, yet has gone through a number of die shrinks as the feature size has been reduced. The die shrink is illustrated in Figure 3. Though the die got smaller, the number of I/O off the die stayed the same. This means the bond pad pitch has to shrink.



Figure 3. Intel Shrinks Pentium  

Pad Pitch

The microcircuit manufacturing process can make pads on 1-micron centers. The useful pitch of a bonding pad is set by the wirebonder technology. This is the major driving force on bonding technology allowing a tighter pad pitch on the chip. Figure 4 shows the maximum number of pads that can fit on a die with a fixed pad pitch. For the largest die, at 18mm on a side, the pad limited I/O count is 720 I/O for 100 micron centers. A growing concern for large ASICs is being pad limited. This means the die size must be artificially increased to allow enough perimeter for all the bonding pads.

Figure 4. Maximum I/O Possible for Pads Limited Peripheral Die
Source: ICE, “Roadmaps of Packaging Technology”


Die Pad/Paddle Design



Acoustic Microscopy Images


The surface texture of Pad/paddle designs that accommodate large die, now common in quad-flatpacks, needs to provide an adhesive enhancing feature to insure adequate strength to withstand the stresses of the solder re-flow process. The stress of solder re-flow temperature from the difference in TCE between the die, the die paddle and the encapsulant, is compounded by the moisture absorption properties of the plastic. The vapor pressures generated at the smooth surface interface are distributed entirely against the die forcing it away from the paddle. This results in a weakening or de-laminating of the die attach interface and poor thermal conductivity is a result. Poor thermal conductivity often results in excessive heating of the die causing electrical parameter failures. Mechanical movement of the die also can result in broken bond wires.

The waffle design in the acoustic microscopy image above is a popular, but more costly, alternative to the plain surface design. The waffle design provides more surface area for better adhesion and allows for some expansion of the vapors during solder re-flow.

Material Issues

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Copper is beginning to be used because it allows the microcircuits to go at higher speeds. The advantage copper has over aluminum is that copper has less resistance and therefore allows electrons to flow faster. This reduces the chip interconnect delays and results in increased speed for semiconductor devices. The use of copper also reduces power consumption. Copper may prove to be a necessity as transistor sizes go to 0.18-micron and beyond. As the circuit size is decreased, the signal-current densities increase and more heat is generated. Copper can support much higher current densities than aluminum because it has a higher melting point. In addition, copper is more reliable than aluminum under the same current densities. Another problem that arises with smaller geometries is crosstalk (the leakage of electrons). Because copper is a better conductor than aluminum it is less likely to leak electrons. Using better dielectric materials with lower dielectric constant (k) values can also alleviate crosstalk. They’re some issues with copper that need consideration:

a.  Copper is difficult to etch. Manufacturers have to change their deposition and etch steps. The industry is adapting the Damascene process in which the interconnect lines and vias are etched to remove the dielectric materials instead of the metal, whereas with aluminum the metal is etched. This switch to dielectric etch from metal etch has created new requirements for etching tools and technology.

b.  The need to deposit the damascene barrier and seed layers before copper deposition is a problem. The purpose of the barrier layer is to prevent the copper from diffusing into the dielectric material and destroying the transistors. The Damascene process starts with a layer of dielectric material that is etched by photolithography to produce the circuit pattern. A barrier layer (typically a few hundred angstroms of refractory titanium or tungsten-nitride) is applied to the etched pattern. On the barrier layer, a very thin seed layer is deposited by physical-vapor deposition to serve as a “primer” on which the copper is laid. Since the few-hundred-angstrom barrier layer is deposited in the circuitry prior to the copper, the barrier layer reduces the height and width of the copper trace; therefore reducing the resulting overall thickness of the copper interconnect. The thinner the copper interconnect is, the higher the resistivity will be and at very fine geometries the barrier layer can have a dramatic impact on the speed of the circuitry.

c.  Depositing microscopic copper interconnects on a microcircuit is very difficult. The problem lies with the high aspect ratios presented by the 0.25 micron and below vias and holes that can have depths as great as 1.0 micron. It is hard to completely fill in the etched pattern in the dielectric and this can result in voids and small cracks in the copper leading to opens in the microcircuit.

d.  Current processes for copper deposition are chemical-vapor-deposition (CVD) and electrochemical plating; they both have problems with the very fine pitch geometry.

e.  Copper does not mix well with current dielectric materials used for aluminum. Copper can diffuse quickly through the insulating oxides (dielectrics) and into the silicon, destroying the transistors (hence, the use of the barrier layer mentioned above).

Signal Propagation

Speeding up signal propagation through the microcircuit can be accomplished by using a dielectric material with a low k. The lower k will speed up the signal by decreasing the charge buildup between the conductive lines. Some issues with new dielectrics that need consideration are detailed below:

a.  The shift to 0.18-µm and smaller process geometries and copper interconnects places new requirements on dielectric materials used in fabrication. With geometries over 0.5µm, silicon dioxide, with a k of about 4, was used successfully to isolate layers of metals. As linewidths have gotten smaller, the use of silicon dioxide is no longer feasible because its relatively high k value creates excessive charge build-up on the metal lines and slows the signal propagation.

b.  The capacitance increases as k increases, and the capacitance increases as the linewidths get smaller. It is important to use low-k dielectrics with small geometry microcircuits. Wire delay increases as a percentage of total delay in the smaller geometries. Manufacturers are using dielectric materials with constants of between 3.0 and 4.0 for their 0.18µm processes. To go to 0.15µm and below, dielectric constants will need to be limited to 3.0 or less.

c.  An ideal low-k material is one that offers a low dielectric constant and has similar properties as silicon-dioxide, such as low leakage, low thermal coefficient of expansion (<10 ppm/C), high dielectric break-down voltage (2-3 MV/cm), low film stress, low water absorption, high cracking resistance, and adhesion to other materials.

d.  Another critical factor is the ability to integrate the low-k materials easily into the manufacturing process. Low-k materials have been difficult and expensive to integrate into production lines and are poor thermal conductors.

e.  Making the material porous can lower the dielectric constant of organic polymers. For example, a polymer with a k value of 2.65 can be modified to have a k value of just about 2.0 by putting 20% porosity in the polymer.

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