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Radiation Hardness Assurance (RHA)

RHA is required for all devices that must operate in a radiation environment. Three distinct situations are possible and each must be addressed separately as follows:

(1)       QML Vendor Technology: Pieceparts are accepted as qualified for the specified RHA level with no additional testing required when die are procured from a qualified QML vendor and application parameter limits lie within the die specification (a QML qualified die fabrication technology). The parts used in the equipment must pass all TCI/QCI test for the specified RHACL of the QML fabrication technology.  

When the specified RHA levels and parameter limits for the qualified die and planned circuit application do not match, additional specification controls are needed. These may best be accomplished with a selected item drawing (SID). 

(2)       Vendor RHA Product Qualification: When pieceparts are procured from a vendor where the supplier maintains die fabrication technology change control, the parts shall be qualified to the RHA level for the required RHA environment. The qualification test requirements shall be based on the requirements of Mil-PRF-38535, Appendix A, for Class B or Class S devices as appropriate for the application. Group "C" steady state life test shall be performed on a sample of each lot of die to establish parameter deltas. Post-radiation temperature and end-of-life deltas shall be established and documented. Qualification shall be reperformed as a result of a major change of the die vendors die fabrication technology. 

(3)       Commercial Vendor Lot Qualification: When pieceparts are procured from a commercial semiconductor supplier who does not guarantee change control of the fabrication process, the equipment supplier shall develop and document a plan to assure fabrication lot uniformity (i.e., same wafer lot, homogeneous lot process, etc.) The plan shall identify a lot sample plan and qualification test for each lot based on the RHA requirements for the equipment. The qualification test requirements shall be based on the requirements of Mil-PRF-38535, Appendix A, type of requirement for Class B or Class S devices as appropriate for the application. Group "C" steady state life test shall be performed on a sample of each lot to establish parameter deltas. Post radiation temperature and end-of-life deltas shall be established and documented. Any fabrication lot exceeding initial established deltas shall be scrapped. 

Parts Control Procurement Plan (PCPP) for RHA Devices 

Since radiation requirements impose additional requirements on the parts control process the basic PCPP will have to be augmented to reflect these requirements. In addition to the normal controls, additional controls are required to establish both the radiation hardness of the device, and the maintenance of this level through the duration of the program. Assurance that the initial hardness level has not changed is a larger effort than establishing the initial level, particularly for the commercial quality system devices.  Additional information is required for RHA devices and applications requiring equipment to operate in a radiation environment.

Effects & Environment
Quality System
Selection Guidance
Application Practice
Element Design
System Guidance


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The correct application of microcircuits is essential to overall performance, hardening and survivability for nuclear and space environments, reliability and cost/availability of systems. This section provides a discussion of the issues that must be addressed to ensure correct part selection for systems with a radiation hardening requirement.

Radiation Hardness Assurance 

The proper operation of microelectronics in a radiation environment requires knowledge and understanding of the radiation environment (e.g., nuclear weapons engendered, earth's magnetosphere, space, man-made commercial, etc.), the performance required of the microelectronics in the environment (e.g., operate-through, etc.), the equipment configuration (e.g., shielding, shadowing, circumvention, etc.), the response of the actual device and the device response in the intended circuit application. The last point is especially important in a nuclear weapons environment (NWE) due to dose-rate and internal electromagnetic pulse (IEMP) effects.

Qualification Requirements 

For the case of the QML supplier the RHACL shall be used to determine the margin between the actual radiation levels and the device capability. For those suppliers who are not QML certified but maintain stringent SPC of the critical design and process parameters, report all design and process changes and have characterization data concerning device, the application of devices use shall be based on radiation test results.

A proposed method to derive the required data base would consist of radiation testing using MIL-PRF-38535, Appendix A, Class Q or Class V requirements (as appropriate to the application), performing steady state life tests on a sample of each lot of die to establish parameter deltas and finally establishing post-radiation temperature and end-of-life deltas. 

In addition, this process should be reperformed following any major change of the vendor’s fabrication methodology. 

For those vendors who provide commercial parts without any guarantee of change control, a lot sample plan or equivalent would have to be developed by the equipment manufacturer to assure fabrication lot uniformity (i.e., same wafer lot, homogeneous lot process, etc.). The plan must identify a lot sample plan and qualification testing procedures. A more detailed description of these requirements is provided in the Selection Guidance section.

Element Design

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This section provides a suggested process for selecting microcircuits with the required performance, reliability and radiation hardness capabilities. The goal of this process is to ensure cost effective designs that satisfy all of the above noted requirements.

General Process 

The parts selection process, as in the non-radiation environment situation, must begin with a clear understanding of the application, including both the electrical performance required and the application environment (e.g. temperature, atmosphere, vibration, etc.). However, for device applications in systems that must operate and survive in a radiation environment, these radiation effects must be superimposed upon the other natural environment conditions.

This latter task is especially significant since the effects of the ambient environment (e.g. temperature, atmosphere, etc.) will impact the radiation response of the microcircuits. 

Radiation Response Variability 

One of the major issues concerning the use of microelectronics for applications which require radiation hardness is the variability of the radiation response of a specific technology and the designs emanating from that technology.

Two specific issues must be considered: 

(1) The sensitivity of the response of a circuit to a particular environment or failure mode (e.g., total ionizing dose, dose-rate, SEE, displacement damage, etc.) due to otherwise acceptable process variations. 

(2) The statistical process controls (SPC) and qualification conformance inspection (QCI) procedures used by a specific semiconductor supplier to maintain critical process/design parameters for radiation hardness. 

In general total ionizing dose response is the most sensitive of the radiation effects to processing parameters. The processing parameter associated with gate oxide and field oxide growth are the most critical. Moreover, relatively small changes in processing temperature, time, pressure, contamination, and atmosphere (e.g., argon vs. nitrogen; steam vs. dry) can have a dramatic effect on final process robustness. Circuit design rules and layout also are important, but not to the same degree as processing  parameters. 

Dose-rate upset, SEE and displacement damage are more affected by piecepart electrical design rules and layout than the process parameters. However, individual transistor response (e.g., current drive and propagation delay) plays an important role concerning dose-rate and SEE response. 

In general, total ionizing dose affects both MOS and bipolar technologies; dose-rate upset and SEE affect MOS, bipolar and GaAs technologies and neutron/proton irradiation (displacement damage) affects bipolar technology and MOS technologies associated with electro-optical devices (e.g., charge-coupled and charge-integrating devices). 

Concerning semiconductor supplier SPC and QCI, the following can be stated: 

· QML Suppliers with specified RHACL's: For these suppliers the radiation sensitive process and design parameters have been identified and kept under strict control. Consequently, minimal variability in circuit (technology) response is the standard. 

· RHA Suppliers: These suppliers are typified by the application of stringent post-fabrication screening and characterization procedures as a method of supplying in-specification products. These suppliers may or may not have identified all critical processing/design parameters, since post-fabrication screening is relied upon to meet specifications. Hence, in some cases, greater variability in radiation response can be anticipated and precautions should be taken to ensure that circuit performance is not compromised when using these circuits. 

· Non-RHA/QML Suppliers: Products provided by these suppliers can be anticipated to have significant variability concerning their radiation response. Hence, stringent characterization, screening and testing is mandatory. 

The subsection on Radiation Hardness Assurance in the section on Selection Guidance provides additional discussion concerning the RHA procedures required for the different classes of semiconductor suppliers. 

Application Specific Integrated Circuits (ASICs) 

The use of ASICs in a radiation environment provides a number of unique challenges for a circuit designer. This occurs since, in addition to the standard effects on radiation response caused by process and design variations, specific personalizations can also impact radiation hardness capability.

Thus, although a robust set of process and design rules may be available for a QML manufacturer, it still may be necessary to perform radiation testing on every personalization of a gate array. 

The requirement to perform testing for specific environments and the complexity of the testing will depend on the margin between the radiation levels of the operating environment and the capability of the technology. 

The need for the testing is, as previously stated, due to the effects the layout, physical interconnections, and the die have on the radiation hardness of a specific ASIC. In the following discussion each of the radiation environments will be discussed. 

(1)       Total Ionizing Dose: The effects of TID in an MOS circuit are in general to reduce operating speed, increase leakage current, reduce individual transistor current drive, and reduce transconductance. Concerning these effects, leakage current and operating speed must be dealt with by the basic process and layout rules. 

However, to ensure satisfactory IC operation circuit design rules that govern transistor fan-in and fan-out, signal and clock routing, etc. must be considered. 

Depending on the design margin, changes in transistor operating speed can result in "race" conditions for specific personalizations. 

In general, simulation and analysis can be used to identify and investigate worst-case signal paths, and based on the design margins, a decision to perform total ionizing dose testing for a specific personalization determined. 

(2)       Dose-Rate-Upset/Survivability: There are two specific issues which strongly suggest that each individual personalization be subjected to dose-rate upset testing. These issues include: 

· The effects of the die power distribution on the upset level of circuits interior to the die. Circuits which are furthest from the input power pins suffer the greatest IR (voltage) drop caused by the dose-rate engendered photocurrents and will be more prone to upset due to rail-span collapse. Thus, these sensitive areas must be identified to ensure worst-case testing. 

· The effects of transistor location on charge collection. The proximity of a transistor or circuit to the edge of a die or to other transistors can significantly affect the amount of photocurrent collected at critical junctions/nodes. 

In addition, circuit design rules concerning fan-out/fan-in and I/O loading can also influence upset levels both at internal nodes and at the outputs. 

Thus, the dose-rate upset performance of a complex ASIC can be significantly affected by the actual layout of the transistors which comprise that circuit. 

The sensitivity of the ASIC to layout will of course be a function of the performance capability of the process/design to the actual threat level or the so-called design margin. 

Here again, the need to perform comprehensive testing can be identified through analysis and simulation. However, the issues of identifying sensitive areas of a die and the input vector set required to exercise those sections of the circuit personalization greatly increase the difficulty associated with both simulation and testing. 

Proprietary simulation codes exist (e.g., BUSNET, a product of Mission Research Corporation) to accomplish this type of analysis and should be used to support any dose-rate upset testing. Also, for testing of this complexity, pretest analysis is mandatory to ensure worst-case situations are accurately identified. 

(3)       Single-Event-Effects: Specific ASIC personalizations can also affect SEE performance and complicate establishing a simple quantifiable metric (e.g., errors per bit/day for a memory) for a particular design. 

Some of the factors that would influence the SEE performance include: 

· The specific operation (i.e., input excitation vectors, and mode of operation, etc) of the circuit in progress at the time of the ion strike will determine the nature of the single event effect. The complexity of this factor can be appreciated if we consider the SEE sensitivity of a microprocessor such as a 486. The specific operation in progress, the data being operated-on, etc. will all affect the overall IC response. 

· The propagation path of an upset. Specifically, a heavy ion strike can result in the creation of a spurious signal at some location in a combinatorial circuit. This signal or glitch can propagate through the circuit until it is attenuated to a level where the signal is no longer capable of causing an upset or until it reaches (i) an output pin and propagates off chip with to-be-determined consequences or (ii) reaches an internal latch with sufficient amplitude and duration to reset the circuit. Once "latched" this spurious signal will then be interpreted as a "real" signal with TBD consequences. 

Here again the basic concerns are somewhat similar to those engendered by dose-rate upset with the exception that the spurious signal is local rather than global. Also, the same type of simulation methods can be used to determine worst-case situations. 

In addition, non-nuclear types of testing such as laser probing can be used to identify sensitive areas within a die and worst-case conditions (e.g., bias voltage, input vector, mode of operation, etc.). 

Thus, for certain critical ASICs, a comprehensive analysis and test qualification program is required to support operation in a radiation environment (e.g., space, etc.). The level of detail and completeness of these tasks will be governed by the technology design margin and criticality of the application. 

Radiation Hardness Considerations 

 Proper application of microcircuits requires a thorough understanding of the radiation environment, the system functions which must be performed and the hardness of the semiconductor devices which are available. 

The effects of radiation on various semiconductor technologies is summarized in Table 1

The specific radiation environments as a function of device application are summarized in Table 2

Finally, Table 3 provides a summary of threat environments vs. threat mitigation methods. 

In general, device design margin can be traded-off against considerations such as shielding, circuit and system design complexity (e.g., circumvention, EDAC, voting, etc.), RHA requirements (e.g., lot testing, individual device screening, etc.) and overall system design complexity. Obviously, the "best" solution is the one which simultaneously achieves the required system performance (including reliability or MTBF) and minimizes total cost of ownership. 

Table 1. Radiation Effects on Semiconductor Technologies. 





Total Ionizing Dose

Natural Environment:
Trapped electrons
and protons in the
earth's magnetosphere





Charge buildup in the

oxide and other

materials used to


semiconductor devices

Metal Oxide Semiconductor (MOS):

- Increased leakage current

- Changes in operating speed

- Parametric and functional failures

Bipolar Transistors:

- Reduced gain

- Increased leakage current

- Parametric and functional failures


- Insensitive

FO and EO:

- Increased attenuation



 Galactic CosmicRays

 Solar Enhanced


 Energetic protons

     and neutrons



Energetic neutrons

- Deposition of

charge insemiconductor devices

through impact of protons or ofheavy ions from GCRs


- Nuclear Reactions

caused by protons and



- Upset

- Burnout

- Gate rupture

- Latchup


- Upset

- Burnout

- Latchup


- Increased CCD dark current

Solar Cells:

- Degradation in efficiency


- Upset

Displacement Damage


Energetic protons and





- Lattice Damage in


Material resulting in trap formation and doping compensation

FO and EOs:

- Increased attenuation

- Loss of efficiency (CTE)

-Increased dark current

Solar Cells:

- Loss of efficiency


- Gain Degradation

FET (Si & GaAs):

- Relatively Insensitive

Bipolar (Si):

- Power & low ft devices more


-Gain reduction and an increase in bulk Si resistance


Prompt Radiation:

Gamma rays

X rays



MOS, Bipolar & GaAs:

- Upset

- Burnout

- Latchup


FO & EO:

- Darkening

- Upset


TABLE 2. Application/Threat vs. Device Requirements. 


Threat Environment

Representative Device Requirements

ICBM & Strategic Interceptor

· Primary:

-          Neutron Irradiation

-          Dose-Rate

-          upset/Survivability

· Secondary

-          Total Ionizing Dose

· Neutron Irradiation >1013 n/cm 2

· Dose-Rates > 108 rad/s

· Total Dose < 10 krad(Si)



Military Surveillance, Navigation

& Communications Satellites (GEO &

1/2 GEO)


(Natural & NWE)

·  Primary

-          Total Dose

-          SEE

-          Dose-Rate-Upset

· Secondary

-          Displacement Damage

(neutrons & protons)

· Total Dose ³ 300 Krad(Si)

· SEE < 10 -10 errors/bit-day

· Dose-Rate < 108 rad/s

· Neutrons < 1012 n/cm 2

Commercial Communications

Monitoring Satellites (natural &


· Primary

-          SEE

-          Total Dose (NWE)

· Secondary

-          Total Dose (natural)

-          Displacement Damage


· SEE < 10-9 errors/bit-dag

· Total Dose ~ 30 krad(Si) NWE

    (LEO) ~ 10 krad(Si) Natural

Tactical Military Systems Including Avionics

· Primary


-          Dose-rate (upset &


        -       SEE (for avionics)

· Secondary

-          Total dose


-          Neutron irradiation

· Dose-Rate: 109 rad/sec

· Neutron irradiation: 1012 n/cm2

· Total Dose: < 5krad(Si)

· SEE: < 10-9 errors/bit-day

Nuclear Reactor Control &

Scientific Systems

· Primary:

-          Neutron irradiation

-          Total dose

· Neutron irradiation: > 1013 n/cm 2

· Total dose: > 100 krad(Si)


TABLE 3. Threat Environment vs. Mitigation Method. 

Threat Environment

Mitigation Methods

· Total Ionizing Dose

· RH Parts

· Shielding - Note that for high energy electrons &

proton   environments shielding is minimally effectivedue to

   bremsstrahlung effects

· Circuit Design

-          Bias for max. gain


-          Upset

-          Latchup

-          Gate Rupture

-          Burnout

· RH Parts (design, layout & material)

· Shielding for protons & neutrons only

· System Design - EDAC, voting, etc.

· Dose-Rate Upset & Survivability

· RH Parts

· Shielding – shield X-Ray  to gamma limit

· Subsystem Design

-          Circumvention

-          Power Strobing

-          Operate-thru

· Displacement Damage

-          NWE (Neutrons)

-          Natural (protons & neutrons)

· RH Parts (high ft Bipolar transistors or FET


· Shielding – for protons

· Circuit Design - bias for minimum neutron degradation

System Guidance

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This section provides guidance concerning RHA, RHM, and RHS on system development issues.

These activities should be initiated as early as possible in the system development cycle to minimize cost and effort. Moreover, these efforts should be integrated to the maximum extent practicable in the system’s testability requirements. 

Indeed, if an aspect of an overall system development activity entails the development and demonstration of a "new" technology, this development effort should also extend to qualification, RHA, RHM, and RHS tasks as appropriate. 

One example of such a situation would be the need to develop a radiation hardened cryogenic microelectronics technology to support a system development. Since the areas of radiation hardening and testing, reliability testing, process qualification, etc. are ill-defined for this type of technology, it would be highly desirable and cost effective to initiate technology qualification, reliability characterization testing, and RHA efforts in conjunction with the basic development tasks. 

Clearly such a proactive approach is also appropriate for devices without radiation requirements. However, the imposition of this additional set of constraints greatly exacerbates the situation. 

Radiation Hardness Assurance and System Radiation Hardening Considerations 

RHA program - The microcircuit RHA program must include an allocation of radiation design margin in the part acceptance specification limits which can be combined with other parameter degradation stresses, such as time and temperature, to assure each system relevant parameter has tolerable end-of-line (EOL) limits. 

As previously stated, the selection of devices for a particular application requires knowledge of the radiation response of that device, a description of the environment, an understanding of the specific device application, and a description of the system/subsystem where the device will be used. 

Electronic pieceparts are normally obtained for a system through the implementation of a parts control plan (see the Selection Guidance section) and an integral part of such a plan is the radiation hardness assurance (RHA) program. The RHA program refers to all of the methods and procedures which control the acquisition to specified radiation performance levels. Specific RHA requirements for various classes of semiconductor suppliers are also discussed in the Selection Guidance section. 

RHA activities are most apparent during the production phase of a program. However, RHA considerations (e.g., parts selection, parts control, etc.) should begin during the initial stage of a program (i.e., concept definition) and pervade all phases of a program. Such an approach should preclude the need to retrofit radiation hardening into a system which can be extremely costly. If radiation hardening is addressed during the initial stages of a systems development the cost of hardening can be less than 5% of the entire satellite cost. 

In addition to RHA, hardness maintenance and surveillance programs are required to ensure that the robustness of a system is not compromised during its operational phase due to incorrect maintenance. 

For suppliers that provide radiation hardened parts, in general all RHA SMDs require devices to be characterized to indicate device capability (not to system survivability) using the following MIL-STD-883 Test Methods 1017, 1019, 1020, and 1021; and ASTM Test Method 1192. 

RHA designators have been developed to allow for the categorization of total ionizing dose capability levels, as follows:

M = 3 X 103 rad(Si)                         F = 3 X 105 rad(Si)

D = 1 X 104 rad(Si)                         G = 5 X 105 rad(Si)

P = 3 X 104  rad(Si)                         R = 1 X 105 rad(Si)

L = 5 X 104 rad(Si)                         H = 1 X 106 rad(Si) 

For example, if a part is characterized to 5 X 104 rads(Si) the part would be listed as a D level part, but if that same part from a different manufacturer shows a capability to 5 X 105 rads(Si), the part would be listed as an R level on the same SMD. 

The other test methods are handled within the MIL-PRF-38535, Group E paragraphs in each detailed specification as required by design or by the purchase order. The Mil-PRF-38535, Group E Table designates the test method, sample size, identify specific technology types that allow certain tests to be eliminated or retained and contain a variety of caveats concerning radiation testing in general. 

It should be noted that the utmost care must be exercised before a specific test is eliminated. This warning is important since some technologies contain parasitic structures sensitive to radiation effects that don't affect the primary structure but are capable of affecting the overall circuit performance. An example of such a situation would be a combined MOS digital circuit and CCD device. In general, an MOS digital structure is insensitive to neutron irradiation, but neutrons can dramatically degrade the operation of a CCD. Thus, the deletion of neutron testing, which is normally allowed for MOS technology, would be inappropriate for this case. 

By providing a fully characterized detailed device specification the user knows the device capability and can make a better judgment on which part best suits his particular application. However, for the situation where a device without an RHA specification is used in a situation where radiation hardness is required, as is often the case, a complete characterization of the device is required for those applicable environments (e.g., total ionizing dose, SEE, etc.) at the anticipated radiation levels. Also, any decisions concerning the appropriateness of the device must include the statistical variations associated with the device response, anticipated/statistical variations in the operating environment (e.g., solar max, solar min, solar flares, etc.) and the actual system parameters (e.g., shielding, shadowing, end-of-life performance needs, allowable number of upsets, etc.).